本专题70多篇英文资料，讲述怎样优化 Pentium CPU 系列处理器代码．This manual describes in detail how to write optimized assembly language code, with particular focus on the Pentium® family of microprocessors.

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MMX 优化: How to optimize for the Pentium family of microprocessors 最新文章

» 28.1 Integer instructions
28 . List of instruction timings for PPlain and PMMX 28.1 Integer instructions Explanations: Operands: r = register, m = memory, i = immediate data, sr = segment register m32 = 32 bit memory operand,...
发表于 2000-04-03

» 28.2 Floating point instructions
28.2 Floating point instructions Explanations: Operands: r = register, m = memory, m32 = 32 bit memory operand, etc. Clock cycles: The numbers are minimum values. Cache misses, misalignment, denormal...
发表于 2000-04-03

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MMX 优化: How to optimize for the Pentium family of microprocessors 所有文章

» 2000-04-03 28.1 Integer instructions
» 2000-04-03 28.2 Floating point instructions
» 2000-04-03 27.6 Using integer instructions to do floating point operations (all processors)
» 2000-04-03 27.10 Detecting processor type (All processors)
» 2000-04-03 27.7 Using floating point instructions to do integer operations (PPlain and PMMX)
» 2000-04-03 31. Comparison of the different microprocessors
» 2000-04-03 28.3 MMX instructions (PMMX)
» 2000-04-03 27.3 Freeing floating point registers (all processors)
» 2000-04-03 27.4 Transitions between floating point and MMX instructions (PMMX, PII and PIII)
» 2000-04-03 30. Testing speed
» 2000-04-03 29.1 Integer instructions
» 2000-04-03 27.8 Moving blocks of data (all processors)
» 2000-04-03 29.2 Floating point instructions
» 2000-04-03 29.4 XMM instructions (PIII)
» 2000-04-03 27.9 Self-modifying code (All processors)
» 2000-04-03 27.5 Converting from floating point to integer (All processors)
» 2000-04-03 29.3 MMX instructions (PII and PIII)
» 2000-04-02 26.2 Rotates through carry (all processors)
» 2000-04-02 26.9 FRNDINT (all processors)
» 2000-04-02 25.1. Loops in PPlain and PMMX
» 2000-04-02 26.3 String instructions (all processors)
» 2000-04-02 25.2 Loops in PPro, PII and PIII
» 2000-04-02 26.8 FPREM (all processors)
» 2000-04-02 26.4 Bit test (all processors)
» 2000-04-02 26.7 FCOM + FSTSW AX (all processors)
» 2000-04-02 26.1 XCHG (all processors)
» 2000-04-02 26.5 Integer multiplication (all processors)
» 2000-04-02 26.10 FSCALE and exponential function (all processors)
» 2000-04-02 26.11 FPTAN (all processors)
» 2000-04-02 26.12 FSQRT (PIII)
» 2000-04-02 26.6 WAIT instruction (all processors)
» 2000-04-02 26.13 MOV [MEM], ACCUM (PPlain and PMMX)
» 2000-04-02 22.5. Replacing conditional jumps by conditional moves (PPro, PII and PIII)
» 2000-04-02 27.2 Division (all processors)
» 2000-04-02 26.14 TEST instruction (PPlain and PMMX)
» 2000-04-02 23. Reducing code size (all processors)
» 2000-04-02 24. Scheduling floating point code (PPlain and PMMX)
» 2000-04-02 26.15 Bit scan (PPlain and PMMX)
» 2000-04-02 26.16 FLDCW (PPro, PII and PIII)
» 2000-04-02 27.1 LEA instruction (all processors)
» 2000-04-01 9. Address generation interlock (PPlain and PMMX)
» 2000-04-01 8. First time versus repeated execution
» 2000-04-01 2. Literature
» 2000-04-01 20. Dependency chains (PPro, PII and PIII)
» 2000-04-01 14. Instruction decoding (PPro, PII and PIII)
» 2000-04-01 15. Instruction fetch (PPro, PII and PIII)
» 2000-04-01 6. Alignmen
» 2000-04-01 21. Searching for bottlenecks (PPro, PII and PIII)
» 2000-04-01 16.1 Eliminating dependencies
» 2000-04-01 4. Debugging and verifying
» 2000-04-01 22.1 Branch prediction in PPlain
» 2000-04-01 22.2 Branch prediction in PMMX, PPro, PII and PIII
» 2000-04-01 How to optimize for the Pentium family of microprocessors
» 2000-04-01 16. Register read stalls
» 2000-04-01 5. Memory model
» 2000-04-01 22.3. Avoiding jumps (all processors)
» 2000-04-01 17. Out of order execution (PPro, PII and PIII)
» 2000-04-01 22.4. Avoiding conditional jumps by using flags (all processors)
» 2000-04-01 1. Introduction
» 2000-04-01 18. Retirement (PPro, PII and PIII)
» 2000-04-01 10.1 Pairing integer instructions (PPlain and PMMX): Perfect pairing
» 2000-04-01 3. Calling assembly functions from high level language
» 2000-04-01 19.1 Partial register stalls
» 2000-04-01 10.2 Imperfect pairing
» 2000-04-01 19.2 Partial flags stalls
» 2000-04-01 11. Splitting complex instructions into simpler ones (PPlain and PMMX)
» 2000-04-01 19.3 Flags stalls after shifts and rotates
» 2000-04-01 7. Cache
» 2000-04-01 12. Prefixes (PPlain and PMMX)
» 2000-04-01 19.4 Partial memory stalls
» 2000-04-01 13. Overview of PPro, PII and PIII pipeline