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29.1 Integer instructions


日期: 2000-04-03 14:00 | 联系我 | 关注我: SteemIT, Twitter, Google+

29. List of instruction timings and micro-op breakdown for PPro, PII and PIII

Explanations:

Operands:

r = register, m = memory, i = immediate data, sr = segment register, m32 = 32 bit memory operand, etc.

Micro-ops:

The number of micro-ops that the instruction generates for each execution port.

p0: port 0: ALU, etc.

p1: port 1: ALU, jumps

p01: instructions that can go to either port 0 or 1, whichever is vacant first.

p2: port 2: load data, etc.

p3: port 3: address generation for store

p4: port 4: store data

Delay:

This is the delay that the instruction generates in a dependency chain. (This is not the same as the time spent in the execution unit. Values may be inaccurate in situations where they cannot be measured exactly, especially with memory operands). The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably. Floating point operands are presumed to be normal numbers. Denormal numbers, NANs and infinity increase the delays by 50-150 clocks, except in XMM move, shuffle and boolean instructions. Floating point overflow, underflow, denormal or NAN results give a similar delay.

Throughput:

The maximum throughput for several instructions of the same kind. For example, a throughput of 1/2 for FMUL means that a new FMUL instruction can start executing every 2 clock cycles.

< TD>
29.1 Integer instructions
InstructionOperandsmicro-opsdelaythroughput
p0p1p01p2p3p4
NOP1
MOVr,r/i1
MOVr,m1
MOVm,r/i11
MOVr,sr1
MOVm,sr111
MOVsr,r85
MOVsr,m718
MOVSX MOVZXr,r1
MOVSX MOVZXr,m1
CMOVccr,r11
CMOVccr,m111
XCHGr,r3
XCHGr,m4111high b)
XLAT11
PUSHr/i111
POPr11
POP(E)SP21
PUSHm1111
POPm5111
PUSHsr211
POPsr81
PUSHF(D)31111
POPF(D)1061
PUSHA(D)288
POPA(D)28
LAHF SAHF1
LEAr,m11 c)
LDS LES LFS LGS LSSm83
ADD SUB AND OR XORr,r/i1
ADD SUB AND OR XORr,m11
ADD SUB AND OR XORm,r/i1111
ADC SBBr,r/i2
ADC SBBr,m21
ADC SBBm,r/i3111
CMP TESTr,r/i1
CMP TESTm,r/i11
INC DEC NEG NOTr1
INC DEC NEG NOTm1111
AAS DAA DAS1
AAD124
AAM11215
MUL IMULr,(r),(i)141/1
MUL IMUL(r),m1141/1
DIV IDIVr821191/12
DIV IDIVr1631231/21
DIV IDIVr3231391/37
DIV IDIVm8211191/12
DIV IDIVm16211231/21
DIV IDIVm32211391/37
CBW CWDE1
CWD CDQ1
SHR SHL SAR ROR ROLr,i/CL1
SHR SHL SAR ROR ROLm,i/CL1111
RCR RCLr,111
RCR RCLr8,i/CL44
RCR RCLr16/32,i/CL33
RCR RCLm,112111
RCR RCLm8,i/CL43111
RCR RCLm16/32,i/CL42111
SHLD SHRDr,r,i/CL2
SHLD SHRDm,r,i/CL21111
BTr,r/i1
BTm,r/i161
BTR BTS BTCr,r/i1
BTR BTS BTCm,r/i16111
BSF BSRr,r11
BSF BSRr,m111
SETccr1
SETccm111
JMPshort/near11/2
JMPfar211
JMPr11/2
JMPm(near)111/2
JMPm(far)212
conditional jumpshort/near11/2
CALLnear11111/2
CALLfar28122
CALLr12111/2
CALLm(near)141111/2
CALLm (far)28222
RETN1211/2
RETNi1311/2
RETF233
RETFi233
J(E)CXZshort11
LOOPshort218
LOOP(N)Eshort2 18
ENTERi,01211
ENTERa,bca. 18+4bb-12b
LEAVE21
BOUNDr,m762
CLC STC CMC1
CLD STD4
CLI9
STI17
INTO5
LODS2
REP LODS10+6n
STOS111
REP STOSca. 5n a)
MOVS1311
REP MOVSca. 6n a)
SCAS12
REP(N)E SCAS12+7n
CMPS42
REP(N)E CMPS12+9n
BSWAP11
CPUID23-48
RDTSC31
IN18>300
OUT18>300
PREFETCHNTA d)m 1
PREFETCHT0 d)m 1
PREFETCHT1 d)m 1
PREFETCHT2 d)m 1
SFENCE d) 1 11/6

Notes:

a) faster under certain conditions: see chapter 26.3.

b) see chapter 26.1

c) 3 if constant without base or index register

d) PIII only.


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