The flags register can also cause partial register stalls:
CMP EAX, EBX INC ECX JBE XX ; partial flags stall
The JBE instruction reads both the carry flag and the zero flag. Since the INC instruction changes the zero flag, but not the carry flag, the JBE instruction has to wait for the two preceding instructions to retire before it can combine the carry flag from the CMP instruction and the zero flag from the INC instruction. This situation is likely to be a bug rather than an intended combination of flags. To correct it change INC ECX to ADD ECX,1. A similar bug that causes a partial flags stall is SAHF / JL XX. The JL instruction tests the sign flag and the overflow flag, but SAHF doesn't change the overflow flag. To correct it, change JL XX to JS XX.
Unexpectedly (and contrary to what Intel manuals say) you also get a partial flags stall after an instruction that modifies some of the flag bits when reading only unmodified flag bits:
CMP EAX, EBX INC ECX JC XX ; partial flags stall
but not when reading only modified bits:
CMP EAX, EBX INC ECX JE XX ; no stall
Partial flags stalls are likely to occur on instructions that read many or all flags bits, i.e. LAHF, PUSHF, PUSHFD. The following instructions cause partial flags stalls when followed by LAHF or PUSHF(D): INC, DEC, TEST, bit tests, bit scan, CLC, STC, CMC, CLD, STD, CLI, STI, MUL, IMUL, and all shifts and rotates. The following instructions do not cause partial flags stalls: AND, OR, XOR, ADD, ADC, SUB, SBB, CMP, NEG. It is strange that TEST and AND behave differently while, by definition, they do exactly the same thing to the flags. You may use a SETcc instruction instead of LAHF or PUSHF(D) for storing the value of a flag in order to avoid a stall.
INC EAX / PUSHFD ; stall ADD EAX,1 / PUSHFD ; no stall SHR EAX,1 / PUSHFD ; stall SHR EAX,1 / OR EAX,EAX / PUSHFD ; no stall TEST EBX,EBX / LAHF ; stall AND EBX,EBX / LAHF ; no stall TEST EBX,EBX / SETZ AL ; no stall CLC / SETZ AL ; stall CLD / SETZ AL ; no stall
The penalty for partial flags stalls is approximately 4 clocks.